The present invention relates to a clock resynchronizer which receives data synchronized with a writing clock and outputs the received data in synchronization with a reading clock in a high-speed digital data communication system. This operation will be hereinafter referred to as clock resynchronization.
When received data and a reading clock inside a circuit differ in speed or phase, a clock resynchronizer is generally used to temporarily store received data composed of an appropriate number of bits and transmit the received data in synchronization with the reading clock so as to avoid overlapping or missing of bits.
For such conventional clock resynchronizers, schemes such as a scheme for detecting a phase difference or a scheme for detecting a start flag have been used. The scheme for detecting a phase difference needs a large circuit scale or a complicated circuit configuration. To solve these problems, a circuit using a start flag is proposed in Japanese Examined Patent Publication (Kokoku) No. 6-56997. This circuit initializes the bit position for read operation by utilizing a series of operations starting with the detection of the start flag.
Hereinafter, the circuit disclosed in Japanese Examined Patent Publication No. 6-56997 will be described.
According to the publication, input data contains: a time-fill inserted between frames of the input data at a cycle represented by a factor of the number of bits corresponding to the capacity of a buffer; and a frame start flag. The circuit disclosed in the publication is an elastic buffer circuit (a clock resynchronizer) which temporarily writes write data, which has been obtained by delaying input data in synchronization with a writing clock, in one of a plurality of buffers selected based on a counted value of the writing clock in the order of arrival of bits, in synchronization with the writing clock. The circuit uses, as output data, data read out from buffers each selected based on a counted value of a reading clock in the order of arrival of bits. The circuit is characterized by including: a latch circuit for holding outputs from the buffers in a given period after the detection of the start flag; and a holding time counter for loading the counted value of the writing clock in a resister as the counted value of the reading clock with the lapse of time within the holding period of the latch circuit.
In the invention disclosed in the publication, a start flag included in a flame in input data is detected, and thereby a bit pattern of a time-fill written in each buffer before the detection is held in a latch circuit during a given time. With a lapse of time in this holding time, the counted value of a writing clock at the time of the detection of the start flag is loaded into a read counter so that at every subsequent increment by the reading clock, bits in the flame of the input data are read out in the order of arrival from each buffer through the latch circuit which is in a through state.
Referring now to FIG. 1 of the publication, an embodiment thereof will be hereinafter described. In a circuit disclosed in this publication, a buffer capacity is composed of n bits. A delay circuit 1 delays input data Di in synchronization with a writing clock CKw. Flip-flops 21 through 2n receive the input data Di (write data Dw) output from the delay circuit 1. On the other hand, the writing clock CKw derived from received data is input to a write counter 3. A counted value output from the write counter 3 is input to an n-bit decoder 4. Output terminals of AND gates 51 through 5n are connected to respective clock input terminals of the flip-flops 21 through 2n. Outputs from the flip-flops 21 through 2n are transmitted to a data selector 7 through the latch circuit 6. The input data Di is input to a start-flag detector 8. The start-flag detector 8 outputs a latch signal S1. The latch signal S1 is input to a register 9 provided at the output side of the write counter 3. A hold signal S2 is connected to a holding time counter 10 and an enable EN of the latch circuit 6.
Referring now to FIG. 2 showing a timing chart of a conventional method of the publication, received data is held in a buffer (flip-flop) during a time predetermined by a hold counter and, after a lapse of the predetermined holding time, data is sequentially read out at every increment by a reading clock.